Generally, in a memory device for storing and reading data such as a dynamic random access memory device, there is installed a circuit for testing a data access operation of memory cell. As the time taken for testing the data access operation is more and more increased since the memory device has a large high integration, a multi-bit text circuit is required to test a plurality of memory cells at the same time. A conventional technique on such a multi-bit test circuit is disclosed in ISSCC (IEEE Journal of Solid State Circuits), Vol. 22, pp 647, 1987.
FIG. 1 is a schematic block diagram showing data input/output portion of the multi-bit test circuit according to the present invention.
Referring to FIG. 1, n data buses D1-Dn are commonly connected to a multiplexer MUX 12 and to a comparator 14, and a test controller 10 is provided for controlling the MUX 12 and the comparator 14. The test controller 10 is enabled by a test enable signal .phi.FTE. The MUX 12 is activated when a write signal WRITE for designating a data writing operation is applied as the logic "high" level, whereas the comparator 14 is activated when a read signal READ for designating a data reading operation is applied as the logic "high" level. The MUX 12 and the comparator 14 are commonly connected to the data input/output ports. The MUX 12 transmits the inputted data to each of the data buses D1-Dn. The comparator 14 compares each logic level of data outputted through the data buses D1-Dn, and then determines whether all the logic levels are same, thereby outputting the determined results as an error flag. Reading and writing circuits connected to data I/O line of a memory cell array are provided to each of the data buses D1-Dn.
FIG. 2 is a circuit diagram illustrating conventional reading and writing circuits. Data bus Di (wherein i=1, 2, . . . n) is commonly connected to a pair of data I/O lines I/O1 and I/O2. Each data I/O line is connected to the data bus Di by parallel connected a reading path and a writing path to each other. The reading path consists of an one-way buffer 16 and a pass transistor 18 for transmitting data from the data I/O line to the data bus Di. In the meanwhile, the writing path consists of an one-way buffer 20 and a pass transistor 22 for transmitting data from the data bus Di to the data I/O line. The gate terminal of the pass transistor 18 on the reading path of the data line I/O1 is controlled by an output from an AND gate 24 which is receiving the read signal READ and a complementary decoded column address signal DAK. In the meanwhile, the gate terminal of the pass transistor 18 on the reading path of the data line I/O2 is controlled by an output from an AND gate 26 which is receiving the read signal READ and the decoded column address signal DAK. Hence, when the read signal READ is applied to the "high" level, one of a pair of data line I/O1 and I/O2 is connected to the data bus Di in accordance with the logic level of the decoded column address signal DAK.
Furthermore, the gate terminal of the pass transistor 22 on the writing path of the data line I/O1 is controlled by an output from an AND gate 28 which is receiving the write signal WRITE and the complementary decoded column address signal DAK. In the meanwhile, the gate terminal of the pass transistor 22 on the writing path of the data line I/O2 is controlled by an output of an AND gate 30 which is receiving an write signal WRITE and the decoded column address signal DAK. Hence, when the write signal WRITE is applied as the "high" level, one of a pair of data line I/O1 and I/O2 is connected to the data bus Di in accordance with the logic level of the decoded column address signal DAK. When one signal of the write signal WRITE and read signal READ is in an activate state, the other signal of them is in a non-activate state.
An explanation on a conventional multi-bit test operation will be given hereinafter with respect to FIGS. 1 and 2. Referring to FIG. 1, the test enable signal .phi.FTE for designating a test mode is applied as the "high" level, the write signal WRITE as the "high" level, and the read signal READ as the "low" level. Thereby, the multiplexer MUX 12 is activated and the comparator 14 is not activated. At this time, if data of the "high" level, for example, is inputted to the multiplexer MUX 12, the multiplexer MUX 12 sets data buses D1-Dn to be the "high" level. Referring to FIG. 2, as the read signal READ is in the "low" level, all the pass transistors 18 positioned on the reading paths of the data lines I/O1 and I/O2 are turned off, while as the write signal WRITE is in the "high" level, one of the pass transistors 22 positioned on the writing paths of the data lines I/O1 and I/O2 is turned on in accordance with the logic level of the decoded column address signal DAK.
For example, if the signal DAK is in the "low" level at the time, the data line I/O1 is connected to the data bus Di. As a result, data being at the "high" level in the data bus Di is transmitted to the data line I/O1 through the one-way buffer 20 and the pass transistor 22, and thereby the data of the "high" level is inputted to a bit line BL1 connected to the data line I/O1. On the other hand, if the signal DAK is changed from the "low" level to the "high" level, the data of the "high" level is inputted to a memory cell designated by a corresponding word line through a bit line BL2 connected to the data line I/O2, through the same process as the data line I/O1 mentioned above,. Since such a writing operation is performed in the reading and writing circuits respectively connected to the data buses D1-Dn, data of the "high" level is transmitted to all of n bit lines, thereby performing the writing operation to n memory cells at the same time.
After a predetermined time is passed, while performing the reading operation, the write signal WRITE is changed to the "low" level and at the same time, the read signal READ is changed to the "high" level. Accordingly, the MUX 12 is not activated and the comparator 14 is activated. Returning to FIG. 2, the pass transistors 22 positioned on the writing path of data lines I/O1 and I/O2 are turned off. Any one pass transistor of the pass transistors 18 positioned on the reading path of data lines I/O1 and I/O2 which has the signals DAK or DAK being at the "high" level is turned on, thereby enabling one of the data lines I/O1 and I/O2 to be connected to the data line Di. At this time, the data line Di is discharged or precharged to a predetermined potential. The memory cell data read through the bit line is transmitted to the data lines I/O1 or I/O2 and is then transmitted to the data bus Di through the reading path. Thereafter, the comparator 14 compares the logic level of data and outputs the results to the error flag. Since such all reading operations are performed in the data buses D1-Dn, the number of data inputted to the comparator 14 is n read out from the n memory cells. Hence, the data reading and writing operation can be performed from/in the n memory cells at the same time. Under the JEDEC standards, the number of data to be tested at the same time in, for example, 64M DRAM is set as 32 bits.
However, there is a case where a testing operation is required for a large number of bits at the same time, in order to meet the requirement for decrement of time taken for testing the data access operation after manufacturing the memory device. In other words, if a user is to test data of 32 bits or 64 bits at the same time, there is a disadvantage in that the conventional technique of FIG. 2 can not perform a testing operation for the number of such data bits.